The present invention is directed, in general, to a semiconductor device and a method of manufacture therefor and, more specifically, to a vertical replacement gate (VRG) metal oxide semiconductor field effect transistor (MOSFET) with a conductive layer adjacent a source/drain region and a method of manufacture therefor.
Enhancing semiconductor device performance continues to be a focus of the semiconductor industry. As a result, both smaller device size and increased performance have been identified as desirable manufacturing targets. As device dimensions within semiconductor devices, such as gates within integrated circuits (ICs), continue to shrink, the method for forming such gates has adapted to effectively accomplish the shrinking devices. However, manufacturing limitations have particularly arisen with respect to the lithographic processes currently used to manufacture such shrunken devices. In fact, current lithographic processes have been unable to accurately manufacture devices at the required minimal sizes. Moreover, this is a limitation that the semiconductor industry, to date, has been unable to correct.
In view of the current limitations in the semiconductor manufacturing lithography process, and the desire to manufacture smaller devices, the semiconductor industry developed a VRG transistor structure. The VRG transistor structure circumvents the limitations associated with the lithographic process discussed above, by keeping each individual device component within functional lithographic limitation and building the devices vertical rather than horizontal on the semiconductor wafer. This allows overall device performance of the semiconductor wafer to be increased without encountering the lithographic limitations discussed above. Unfortunately, however, these VRG structures often have high sheet resistance associated with their structures. Currently, a high dose implant (1E15) is used to form the drain of the VRG structure. Typically, the implant produces a sheet resistance of about 50 xcexa9/square. However, this relatively high drain sheet resistance significantly slows down the device static and high-frequency performance, due to the large conducting distance from the drain extension to the drain metal contact, in the VRG structure. The slow down of the device produces an undesirable slow down in the device speeds. The semiconductor manufacturing industry attempted to increase the high dose implant to an amount greater than 1E15; however, the industry encountered activation problems within the drain, which resulted from the extremely high dose implant.
Accordingly, what is needed in the art is a vertical replacement gate (VRG) metal oxide semiconductor field effect transistor (MOSFET) that can be used to maintain shrunken device size and increased packing density, while avoiding the slow device speeds as encountered in the prior art. The present invention addresses this need.
To address the above-discussed deficiencies of the prior art, the present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the first source/drain region, a second source/drain region and a conductive channel that extends from the first source/drain region to the second source/drain region. The conductive layer provides an electrical connection to it the source/drain region. In a preferred embodiment, the conductive layer has a low sheet resistance that may be less than about 50 xcexa9/square, and preferably less than about 20 xcexa9/square, to the first source/drain region. In another embodiment, the VRG structure further comprises a gate located over the conductive layer with the second source/drain region being located adjacent the gate and the conductive layer. In another one embodiment, the conductive channel has a first source/drain region extension and a second source/drain region extension.
Thus, in one aspect, the present invention provides a VRG structure with a conductive layer that is electrically connected to the source/drain region and provides electrical connection to the source/drain region that allows the VRG structure to operate in a more rapid and efficient manner.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention are described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.